The present invention relates to a testing apparatus and testing method for semiconductor integrated circuits, more specifically a testing apparatus and testing method for semiconductor integrated circuits which have high observability and can readily detect presence and absence of delay faults and stuck-at faults.
Today, semiconductor integrated circuit devices using CMOS logic circuits are widely used. Such semiconductor integrated circuit devices are required to have prescribed performances, and are tested after fabricated as to whether or not they have satisfied the prescribed performances.
In a semiconductor integrated circuit, a path through which signals are propagated is called a path and a delay time from an input signal line, which is a start of the path to an output signal line, which is a terminal of the path is called a path delay time.
Recently, as operational speeds of semiconductor integrated circuits are increased, it is increasingly necessary to measure the path delay time of the semiconductor integrated circuits.
In a conventional path delay fault testing method, in order to detect a delay fault, based on an increase of a path delay time of a path under test, the logic gates of the path under test are activated to propagate a signal transition generated in an input signal line of the path under test to an output signal line of the path under test. Here, xe2x80x9cactivationxe2x80x9d is to switch on all the logic gates of a path under test.
When a delay time of a path under test is longer than a prescribed time, it is judged that the path under test has a path delay fault, and when the delay time of the path under test is shorter than the prescribed time, it is judged that the path under test has no path delay fault.
However, in such a conventional path delay fault testing method, a signal transition generated in an input signal line of a path under test must be propagated to an output signal line of the path under test, and a path under test which can_@not propagate a signal transition to the output signal line cannot be tested. That is, the conventional path delay fault testing method has low observability.
In the conventional path delay fault testing method, to activate a path under test, non-control input values must be inputted to all side inputs which are not on the path under test. It is difficult to satisfy such requirement. Here, a side input is an input line which is not on a path under test. A non-control input value is a logic value which does not uniquely determine an output of each logic gate. For example, non-control input values of an AND gate and a NAND gate are logic value xe2x80x9c1xe2x80x9d, and non-control input values of an OR gate and a NOR gate are logic value xe2x80x9c0xe2x80x9d.
In the conventional path delay fault testing method, the above-described restriction is applied to input values to be inputted to side inputs. Accordingly, it is difficult to generate two test patterns which activate a path under test, i.e., a series of test patterns (a test vector pair).
In the conventional path delay fault testing method, it is necessary that hazards (beard-like pulses) are not generated in side inputs so that hazards (beard-like pulses) are not outputted to an output signal line. It is difficult to set side inputs so as to satisfy such condition.
On the other hand, quiescent power supply current testing method (IDDQ testing method) is proposed as a testing method which has high observability and can easily generate test patterns. The IDDQ testing method does not measure a power supply current in a transient state of a semiconductor integrated circuit, but measures a power supply current in a stable state of the semiconductor integrated circuit. Accordingly, the IDDQ testing method cannot measure a path delay time. In other words, the IDDQ testing method mainly tests absence and presence of a bridge defect of a semiconductor integrated circuit, and cannot detect an open defect and a parametric defect which are primary factors of a delay fault, i.e., abnormalities of process parameters in the fabrication process.
As a method substituting the IDDQ testing method, a testing method (IDDT testing method) which measures a transient current value of a power supply current, i.e., an instantaneous value of a transient power supply current has been proposed. The IDDT testing method is described in, e.g., M. Sachdev, P. Janssen and V. Zieren, xe2x80x9cDefect Detection with Transient Current Testing and its Potential for Deep Sub-micron ICsxe2x80x9d, Proceedings of IEEE International Test Conference, pp. 204-213, 1998. Sachdev et al. evaluate the IDDT testing method as a method substituting the IDDQ testing method, and describe that the IDDT testing method is applicable to fabrication tests for deep sub-micron VLSIs. They describe based on results of the experiment that the IDDT testing method can detect faults of devices having high levels of background current. They do not refer to a testing method for path delay
Recently, as semiconductor integrated circuits are more integrated, paths under test are on increase. Furthermore, circuit modules of semiconductor integrated circuits are buried at deep layer-levels, which makes it additionally difficult to measure a delay time of the path under test. In order to solve such problems, it has been proposed to design a semiconductor integrated circuit such that a part or all of flip-flops of the semiconductor integrated circuit can be scanned, and contents of the flip-flops can be sequentially read out by external control. In this case, a number of clocks are required to read out the contents of the flip-flops. A test time is accordingly long.
Recently, as semiconductor integrated circuits are more integrated, paths under test for path delay time are on increase. It takes long time to measure the path delay time. Accordingly, increase of the test cost is a recent problem.
Accordingly, a testing method which, for saving test costs, can measure efficiently path delay time of semiconductor integrated circuits, has high observability of path delay time and can easily generate test patterns has been expected.
Furthermore, micro-open defects and resistive open defects are problems. A micro-open defect is a very small line breaking defect taking place in a signal line. A very small amount of tunnel current flows through the micro-open defect. A resistive open defect is a defect in which contact resistance between signal lines becomes higher due to a defective contact than a normal value, and a resistance value of the signal lines becomes higher due to breakage of the signal lines. Current flowing through a resistive open defect becomes smaller than a normal value. When a micro-open defect or a resistive open defect is present in a signal line or others, a transition time of a signal is increased, and accordingly a path delay time becomes longer. A micro-open defect and resistive open defect often increase current flowing through a circuit, and accordingly increase power consumption. Thus, the micro-open defect and resistive open defect are detrimental to realizing semiconductor integrated circuit devices of high speed and low electric power consumption. However, the conventional testing methods cannot efficiently detect the micro-open defect and resistive open defect.
An object of the present invention is to provide a testing apparatus and testing method for semiconductor integrated circuits, which have high observability and can readily detect delay faults, stuck-at faults, etc.
The above-described object is achieved by a testing apparatus for a semiconductor integrated circuit comprising: test pattern inputting means for inputting to the semiconductor integrated circuit a test pattern sequence for activating a path under test of the semiconductor integrated circuit; transient power supply current measuring means for measuring transient power supply current supplied to the semiconductor integrated circuit while the path under test is being activated; and fault detecting means for judging absence and presence of a fault in the path under test, based on the transient power supply current measured by the transient power supply current measuring means. Absence and presence of a delay fault and a stuck-at fault can be easily detected with high observability.
In the above-described testing apparatus for a semiconductor integrated circuit, it is preferable that the transient power supply current measuring means measures a width of a waveform of the transient power supply current; and the fault detecting means judges presence of a delay fault in the path under test when the width of the waveform of the transient power supply current is larger than a standard width of a waveform of transient power supply current, which is an expected value of the path under test, by a prescribed value.
In the above-described testing apparatus for a semiconductor integrated circuit, it is preferable that the transient power supply current measuring means measures a width of a waveform of the transient power supply current; and the fault detecting means judges that a stuck-at fault is present in the path under test when the width of the waveform of the transient power supply current is smaller than a standard width of a waveform of transient power supply current, which is an expected value of the path under test, by a prescribed value.
In the above-described testing apparatus for a semiconductor integrated circuit, it is preferable that the transient power supply current measuring means includes a capacitor for supplying power supply current to the semiconductor integrated circuit, and measures a time differential value of a voltage applied to the semiconductor integrated circuit by the capacitor to thereby give a waveform of the transient power supply current.
In the above-described testing apparatus for a semiconductor integrated circuit, it is preferable that the transient power supply current measuring means measures an instantaneous value of the transient power supply current at a timing which is later than a standard delay time, which is an expected delay time of the path under test, by a prescribed time; and the fault detecting means judges that a delay fault is present in the path under test when an instantaneous value of the transient power supply current at the timing is larger than a threshold value which allows judgement that the transient power supply current is being supplied to the semiconductor integrated circuit.
In the above-described testing apparatus for a semiconductor integrated circuit, it is preferable that the transient power supply current measuring means measures a value of the transient power supply current at a timing which is earlier than a normal delay time, which is an expected delay time of the path under test, by a prescribed time; and the fault detecting means judges that a stuck-at fault is present in the path under test when a value of the transient power supply current at the timing is smaller than a threshold value which allows judgement that the transient power supply current is being supplied to the semiconductor integrated circuit.
In the above-described testing apparatus for a semiconductor integrated circuit, it is preferable that the transient power supply current measuring means includes a capacitor for supplying power supply current to the semiconductor integrated circuit, and measures a time differential value of a voltage applied to the semiconductor integrated circuit by the capacitor to thereby give an instantaneous value of the transient power supply current.
In the above-described testing apparatus for a semiconductor integrated circuit, it is preferable that the transient power supply current measuring means measures an integral value of the transient power supply current; and the fault detecting means judges that a delay fault is present in the path under test when the integral value of the transient power supply current is larger than an integral value corresponding to a standard delay time, which is an expected delay time of the path under test, by a prescribed value.
In the above-described testing apparatus for a semiconductor integrated circuit, it is preferable that the transient power supply current measuring means measures an integral value of the transient power supply current; and the fault detecting means judges that a stuck-at fault is present in the path under test when the integral value of the transient power supply current is smaller than an integrated value corresponding to a standard delay time, which is an expected delay time of the path under test, by a prescribed value.
In the above-described testing apparatus for a semiconductor integrated circuit, it is preferable that the transient power supply current measuring means measures an integral value of the transient power supply current; and the fault detecting means judges that a micro-open defect or resistive open defect is present in the path under test when the integral value of the transient power supply current is larger than an integral value corresponding to a standard delay time, which is an expected delay time of the path under test, by a prescribed value.
The above-described object is achieved by a testing method for a semiconductor integrated circuit comprising: inputting a test pattern sequence for activating a path under test of a semiconductor integrated circuit, and judging absence and presence of a fault in the path under test, based on transient power supply current supplied to the semiconductor integrated circuit while the path under test is being activated.
In the above-described testing method for a semiconductor integrated circuit, it is preferable that absence and presence of a delay fault or a stuck-at fault in the path under test is judged by comparing a width of a waveform of the transient power supply current with a standard width of a waveform of transient power supply current, which is an expected value of the path under test.
In the above-described testing method for a semiconductor integrated circuit, it is preferable that absence and presence of a delay fault or a stuck-at fault in the path under test is judged by comparing an instantaneous value of the transient power supply current at a timing which is later or earlier by a prescribed time than a standard delay time which is an expected delay time of the path under test, with a threshold value which allows judgement that transient power supply current is being supplied to the semiconductor integrated circuit.
In the above-described testing method for a semiconductor integrated circuit, it is preferable that absence or presence of a delay fault, a stuck-at fault, a micro-open defect or a resistive open defect in the path under test is judged by comparing an integral value of the transient power supply current with an integral value corresponding to a standard delay time which is an expected delay time of the path under test.
The above-described object is achieved by a delay time measuring apparatus comprising: test pattern inputting means for inputting a test pattern sequence for activating a path under test of a semiconductor integrated circuit to the semiconductor integrated circuit; transient power supply current waveform measuring means for measuring a width of a waveform of transient power supply current supplied to the semiconductor integrated circuit while the path under test is being activated; and delay time measuring means for measuring a delay time of the path under test, based on the width of the waveform of the transient power supply current measured by the transient power supply current waveform measuring means. A path delay time of a path under test can be measured easily with high observability.
The above-described object is achieved by a method for measuring a delay time comprising: inputting a test pattern sequence for activating a path under test of a semiconductor integrated circuit to the semiconductor integrated circuit; and measuring a delay time of the path under test, based on a width of a waveform of transient power supply current supplied to the semiconductor integrated circuit while the path under test is being activated. A path delay time of a path under test can be measured easily with high observability.
As described above, according to the present invention, a path delay time of a path under test can be measured easily by giving a pulse width of a transient power supply current waveform. Furthermore, according to the present invention, a waveform of transient power supply current, which is easy to measure, is measured, which more facilitates the path delay time measurement than the path delay time measurement using voltage signals.
According to the present invention, a waveform of transient power supply current is measured, whereby a path under test which cannot output outside an output signal can be tested. In addition, according to the present invention, the test can be made by inputting an arbitrarily generated series of test patterns, whereby the testing method can be simply made. According to the present invention, there is no special restriction to input values of side inputs, whereby the test can be simply made.
According to the present invention, absence and presence of a delay fault of a path under test can be detected by giving a pulse width of a waveform of transient power supply current, comparing the pulse width with an upper limit value of an allowable delay time. Furthermore, according to the present invention, when a test pattern which can activate a plurality of paths is available, delay faults of the plural paths can be simultaneously detected.
According to the present invention, absence and presence of a stuck-at fault of a path under test can be detected by giving a pulse width of a waveform of transient power supply current, and comparing the pulse width to a value taking into account variations of a fabrication process.
According to the present invention, an instantaneous value of transient power supply current of a prescribed timing is used to evaluate a delay fault and stuck-at fault, whereby absence and presence of a fault of a path under test of a semiconductor integrated circuit can be easily judged.
According to the present invention, absence and presence of a delay fault and stuck-at fault of a path under test of a semiconductor integrated circuit can be easily detected by using an integral value of transient power supply current to thereby detect a delay fault.